Cell Mismatch


Mismatch losses in PV modules occur when the I-V characteristics of the individual cells are significantly different. Mismatch losses occur due to a mismatch between output currents of the solar cells in the PV module. This is because current of a string is limited by the current of the lowest-current cell in a series interconnection. Often, this is caused by shading of cells, or if cells in a module are defective. Mismatch losses include power dissipation in the underperforming cells which lead to hot spots and eventual damage to the module if the heating is consistent. Mismatch losses can also occur in strings of modules in arrays. Bypass diodes are used to mitigate the effects of mismatch losses by limiting the power dissipation in the underperforming cells. However, the occurrence of mismatch issues is still a relevant issue and measures are taken to avoid these losses. These measures include better system design to ensure modules of the same strings receive the same amount of light and to avoid shading. At the manufacturing level, binning is also used to make sure cells of the same electrical characteristics are placed in the same module.

Learning Objectives

  • Understand how mismatch occurs in modules
  • Be able to perform experiments to observe some causes of mismatch
  • Understand how the causes of mismatch may be mitigated
  • Be able to perform experiments to observe how the effects of mismatch can be mitigated

Tutorial Exercise

SunSolve v5 features a Cell JV outputs tab when simulating a PV module. This feature allows users to observe the performance of the individual cells. Their JV characteristics are also tabulated as if they were not connected. By simulating PV modules into situations where mismatch may occur, the Cell and Module JV tabs can be used to investigate the effects of mismatch. You will be using the 72-cell mono-facial module template for this tutorial. For extra reading, refer to the relevant PVmanufacturing.org pages.


Make sure to save and organise any templates/simulations as you proceed throughout this tutorial, any unsaved progress will be lost if the SunSolve page is closed/changed/refreshed.

Part One – Observing Mismatch

Currently, mismatch can be simulated on SunSolve by setting a high zenith angle, causing the module frame to shade the cells on the edge of the module. In this section, you will set a high zenith angle for a simulation with the 72-cell mono-facial module template and observe the effects of mismatch. The Module JV tab provides outputs with and without mismatch, you can use this feature to investigate the effects of mismatch on JV performance.

The responses you will observe are listed in Table 1 below, you will also investigate the JV curves of the module.

Table 1 - List of responses to be observed in Part One
Maximum Power (Pmp) [output and output with no mismatch]W
Fill Factor (FF) [output and output with no mismatch]-
Short circuit current density (Jsc) of the best and worst cell [with cell ID]mA/cm2

Conducting the Experiment

  1. Open a new 72 cell mono-facial module template
  2. Under illumination, set the zenith angle to 84º
  3. Using the sweep function, sweep the azimuth angle from 0º – 180º with 7 equal intervals. SunSolve should automatically set the 30º intervals
  4. Click run and save your completed simulation
  5. Record the 6 responses listed in Table 1 above. When using the Cell JV tab, click the “Relative to average” tick box to view the percentage differences and “Display cell IDs” to obtain the Cell IDs
  6. Average the mismatch difference for the Pmp and Jsc
  7. Sketch scatter plots of the Pmp and FF responses vs the azimuth angle, plotting the mismatch and no mismatch outputs on the same axes
  8. Copy and plot the figure data for the 0º, 90º and 180º azimuth module JV curves


  1. Compare the module JV curves you saved. Describe the change in shape for the first 2 curves and why this shape does not occur in the 90º azimuth curve.
  2. What would cause the change in shape of the IV curve?

Part Two – Mismatch and Bypass Diodes

In Part One, you should have observed how shading different cells of a module causes mismatch and how the different angles of shading changed the effects of mismatch. Most importantly, you should have realised when the bypass diodes were activated. In this exercise, you will observe what occurs when these bypass diodes are removed from the module. The responses listed in Table 1 will be used in the exercise.

Conveniently, the electrical solver can be rerun without using more rays, this will save on the use of rays for this exercise. The electrical solver automatically reruns once any changes have been made to the electrical section of the inputs. Therefore, you must take extra care in saving and organising your simulations before making changes to the circuit.

Conducting the Experiment

  1. Open a new 72 cell mono-facial module template
  2. Under Illumination, set the zenith angle to 84º
  3. Sweep the azimuth for just 0º and 90º
  4. Under Circuit, click on the bypass diodes to remove them from the module
  5. Run the simulation and record the responses listed in Table 1
  6. Copy and plot the Module JV data
  7. Use the Inputs -> Info tab to change the name and description of your simulation and save it accordingly
  8. Repeat steps 4-7 with the same simulation (after saving) but with 1 diode on the right. Under Outputs -> Module JV, click “-> Rerun electrical solver” after the bypass diodes are set correctly
  9. Repeat steps 4-7 with the same simulation (after saving) but with 1 diode in the middle
  10. Repeat steps 4-7 with the same simulation (after saving) but with 1 diode on the left


  1. Compare your module with all 3 bypass diodes in Part One to your module with no bypass diodes. Which module performs better, why?
  2. If the above 2 modules could experience hot spot heating, what would you expect to occur in the underperforming cells? Therefore, which module would perform better? Why?
  3. When the azimuth is set to 0º, which bypass diode is activated?
  4. When the azimuth is set to 90º, which bypass diode is activated?

Part Three – Further Understanding of Mismatch

The following questions are used to make sure that you understand the concepts involved. You can prepare your answers while completing the above tasks

  1. Describe how a shaded cell may cause power dissipation at the cell?
  2. What damage may be caused to a module due to hot spot heating?
  3. Is mismatch more detrimental for cells in parallel or series?
  4. How do bypass diodes reduce the power losses in mismatching cells?
  5. When bypass diodes are activated, is the module voltage or current reduced? Why?
  6. Sketch example IV curves to visualise the process of mismatch losses and mitigation with bypass diodes. Use 10 cells with Isc = 1A and Voc = 0.5V to illustrate the process.
  7. Based on the above exercises and questions, explain what binning is and why it is an important aspect of PV module manufacturing.
  8. What characterisation tools are used for binning?
  9. In an array, are bypass diodes also important for strings of modules? Explain.