PVFactory 5 – Edge Junction Isolation by Plasma Etching


Most phosphorus diffusion processes will lead to phosphorus diffusing into all surfaces of the wafers including the rear surface and the edges. To prevent the photogenerated electrons collected by the front junction from flowing down the phosphorus-diffused edges of the wafers to the rear surface where they are effectively lost, it is necessary to isolate the junction to the front surface of the wafer. One approach used to achieve this isolation is to use a plasma to etch away the unwanted phosphorus-diffused silicon at the wafer edges. This is normally accomplished by first chemically removing residual native or diffusion oxides and then  “stacking” the wafers, in a similar fashion to the way coins are stacked in a pile. The stacked wafers are then placed in a plasma chamber where the exposed edges of the stacked wafers are etched by the plasma.

Learning Objectives

  • Explain why edge junction isolation is a necessary step
  • Be able to perform a single factor experiment to optimise the acidic texturing process
  • Understand how to determine whether the emitter has been satisfactorily isolated
  • Understand how to use a 2-diode model and pseudo I-V analysis to determine J01 and J02 losses in a solar cell
  • Be able to describe different ways in which the emitter can be isolated from the rear contact of a screen-printed solar cell

Tutorial Exercise

Please review the PVmanufacturing pages on Edge Junction Isolation and the help files in PV Factory before attempting the tutorial so that you understand the effect of the different parameters. For this tutorial exercise you will use the ‘Factory Default’ settings for all processes following the Edge Junction Isolation step so leave your UNSW Screen-Print line settings to “Use factory default”. All experiments should use batches of wafers (at least 10 per batch) with the following properties:

  1. Standard Cz mono-crystalline silicon wafers;
  2. 200 mm thick;
  3. Resistivity of 1 W cm; and
  4. Cut using a standard wire saw (this assumes a wire saw that uses a slurry not diamond tips).

In this exercise you should use your best recipes that you have established for the previous steps. To load these recipes use the “L” icon on the left-hand screen when you are processing that step for batches. Otherwise, you can set your user settings to “Use my recipe”, provided the steps following edge isolation are PVfactory default. When you get to the Edge Junction Isolation step, enter your settings, and run that step. To determine the effect of your edge isolation on your cell efficiency, select Run Remaining Steps. This will cause your batch to be processed using the Factory Default parameters for all the remaining steps (because you have not established Best Recipes for these steps yet). The I-V results for your batch will then be available.

Part 1 – Single Factor Response Curves

Because there are only two parameters to optimise in this process there is no need to perform a main factor response experiment as you have done in the previous weeks. For each of etching power and etching time perform a single factor experiment of at least 8 experimental batches (with at least 10 wafers per batch). For each experiment record the following 5 responses:

  1. Shunt resistance (Rsh);
  2. Recombination current density for the n=2 diode (J02);
  3. Pseudo fill factor (pFF);
  4. Open circuit voltage (VOC); and
  5. Mean cell efficiency.

You will need to use the I-V analysis in the Characterisation Lab for the first 3 responses. PV Factory performs a 2-diode analysis of the selected cell and displays a scaled Suns-Voc and the I-V curve. The extracted parameter values are displayed below the graphs. Make sure you understand the analysis that is performed.

To ensure that you have investigated the relationships thoroughly you might want to perform a single factor response curve for a “low” and “high” value of the other parameter. For example, if you were evaluating the effect of etching time, you might want to perform the analysis for a power of 500 and 1500 W

By now you should be able to ensure that you are not breaking too many cells. Also because you have probably processed many cells now it is a good idea for you to check that you are still removing enough of the damaged silicon from the wafer surfaces. What should you do if you are not etching sufficient silicon from each surface?


  1. Produce graphs for each response for each factor. You can use secondary axes to reduce the number of graphs required.
  2. Describe the relationships between your factor and each of the responses.
  3. Store your best recipe in PV Factory.

Part 2 – Understanding Edge Junction Isolation

The following questions are used to determine your understanding of the edge isolation process. You may prepare your answers while completing the above tasks

 General questions:

  1. What is the purpose of the plasma etching?
  2. Under what conditions would you expect a cell’s VOC to be reduced by a poorly-managed edge isolation process?
  3. What is a pseudo I-V curve and how is it measured?
  4. How is the Suns-Voc curve scaled?
  5. What process has now largely replaced plasma etching and explain the advantages of the new process

True/False questions:

  1. Most phosphorus diffusion processes used commercially lead to phosphorus diffusing into the front and the rear surface as well as the edges.
  2. The phosphorus at the edge of the wafer introduces some edge leakage losses, which can be modelled in the solar cell equivalent circuit as a ‘high series resistance’.
  3. Normally any native oxide or residual diffusion oxide (PSG) is removed prior to the plasma etching.
  4. If the etching time is too long, there is a tendency for the ionic species to attack the front and rear surface in the vicinity of the edge.
  5. Inappropriate power and/or etching time can introduce damage to some regions of the front junction resulting in an increased recombination current that is evident in a reduced pseudo FF.
  6. Higher Rsh values typically result when using a chemical rear etch junction isolation process.