The QSSPC measurement on lifetime structure samples can also implicitly estimate the open circuit voltage (V0c) at the early stages of fabrication [1]. This factor is known as the implied V0c (iV0c). Using the relationship between the carrier concentration and voltage, the iVoc for a p-type wafer can be expressed as:

V_{0c}\ =\left(\frac{kT}{q}\right)ln{\left(\frac{\mathrm{\Delta n}\left(0\right)\times\left[N_A+\mathrm{\Delta n}\left(0\right)\right]}{n_i^2}\right)},  (1)

where T is the sample temperature, k is the Boltzmann constant, q is the elemental charge, ni is the intrinsic carrier concentration in silicon and Δn(0) is the carrier concentration at the junction and NA is the substrate doping. Typically, the iV0c value represents an upper limit for the device, since it does not take into account metal-silicon recombination losses, which may be incurred in further processing steps.


Figure 1: Photograph of a silicon wafer solar cell on a Sinton Instruments Suns-Voc stage.

[1] – Cuevas A, Sinton RA. Prediction of the open-circuit voltage of solar cells from the steady-state photoconductance. Progress in Photovoltaics: Research and Applications 1997; 5: 79-90. Available:<79::AID-PIP155>3.0.CO;2-J